10. Heterogeneous Computing: Multi-Chip Scheduling
Chapter focus: In the era of multi-chip, multi-stack coexistence, the difficulty of heterogeneous computing lies less in "installing" than in "scheduling smoothly". This chapter covers four high-frequency engineering problems: driver/CUDA environments, GPU partitioning (MIG/MPS), CUDA-ecosystem migration for domestic accelerators, and Slurm heterogeneous scheduling.
🧭 Reading Map
- Prerequisites: 09. Deep Learning Frameworks — above framework abstractions, heterogeneous hardware differences
- Role: closing chapter of Part 2, L2 — CUDA toolchain, MIG partitioning, multi-vendor mixing, domestic accelerator porting
- Order: CUDA toolchain (install/MPS) → resource partitioning (MIG) → heterogeneous scheduling → domestic porting
- Next: 11. Pre-trained Models — heterogeneous base ready, build large models
Articles
Start with environment setup and GPU partitioning (MIG/MPS); scheduling readers go to Slurm heterogeneous scheduling; migration readers go to domestic-accelerator porting.
Key Takeaways
The core of heterogeneous scheduling is "letting each chip run what it does best": raise small-task density with MIG/MPS, isolate architectures with Slurm partitions, and lower multi-stack maintenance with unified toolchains.