01. AI Hardware & Chips

Chapter focus:

🧭 Reading Map

• Prerequisites: 15. AI Infra Quant (optional, do the math first)
• Role: opening of Part 1, L1 hardware — chips, server topology, firmware and driver lifecycle are the physical preconditions for cluster/network/storage chapters
• Order: chip overview first, then topology → firmware/BIOS → driver lifecycle → liquid cooling
• Next: 03. Cluster Architecture — from single node to cluster, verify hardware with benchmarks

Articles

AI Accelerator Overview: Architecture, Generations & Selection

The three pillars of AI accelerators (Tensor Core compute / memory bandwidth / interconnect bandwidth), A100→H100→H200→B200 generational comparison, and a selection matrix for training, inference, and scientific computing.

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10K-GPU Cluster Hardware Selection & Acceptance Checklist

Five-dimension selection (compute, memory, interconnect, storage, power) for 10K-GPU clusters; a four-step acceptance method: HPL compute, Stream bandwidth, interconnect measurement, 72-hour stability; plus a ready-to-use checklist.

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GPU Drivers & Lifecycle Management: Version Strategy and Upgrade Troubleshooting

CUDA driver version matrix, gray upgrade and rollback for production clusters, Fabric Manager and NVLink health checks, Xid/ECC error monitoring, and hardware lifecycle management.

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GPU Server Hardware Topology: PCIe, NVLink and NVSwitch Interconnect

Reproducible commands dissecting GPU server hardware interconnect: PCIe topology and bandwidth ledger, NVLink/NVSwitch full-mesh, real topology via lspci, performance constraints and selection takeaways.

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Liquid-Cooled Data Center Design: From Air-Cooling Limits to Cold Plates

AI rack power density and air-cooling limits, cold-plate vs immersion selection, CDU/quick-connects/coolant key components, leak detection and operations, with design parameter quick reference.

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GPU Server Firmware & BIOS Tuning: The Last Mile Before Delivery

firmware baseline hardening, BIOS key items, and delivery self-checks.

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GPU's AI Reinvention: Tensor Cores & NVLink

How Tensor Core generations multiplied theoretical FLOPs ~10×, how NVLink/NVSwitch stitch cards into one GPU.

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